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general description the max8795a includes a high-performance step-up regulator, two linear-regulator controllers, and five high- current operational amplifiers for active-matrix, thin-film transistor (tft), liquid-crystal displays (lcds). also included is a logic-controlled, high-voltage switch with adjustable delay. the step-up dc-dc converter provides the regulated supply voltage for the panel source driver ics. the con- verter is a high-frequency (1.2mhz) current-mode regu- lator with an integrated 20v n-channel mosfet that allows the use of ultra-small inductors and ceramic capacitors. it provides fast transient response to pulsed loads while achieving efficiencies over 85%. the gate-on and gate-off linear-regulator controllers provide regulated tft gate-on and gate-off supplies using external charge pumps attached to the switching node. the max8795a includes five high-performance operational amplifiers. these amplifiers are designed to drive the lcd backplane (vcom) and/or the gamma- correction divider string. the device features high out- put current (130ma), fast slew rate (45v/s), wide bandwidth (20mhz), and rail-to-rail inputs and outputs. the max8795a is available in a lead-free, 32-pin, thin qfn package with a maximum thickness of 0.8mm for ultra-thin lcd panels, as well as in a 32-pin lqfp package with 0.8mm pin pitch. applications notebook computer displays lcd monitor panels automotive displays features 2.5v to 5.5v input supply range 1.2mhz current-mode step-up regulator fast transient response to pulsed load high-accuracy output voltage (1%) built-in 20v, 3a, 0.16 ? n-channel mosfet high efficiency (85%) linear-regulator controllers for v gon and v goff high-performance operational amplifiers ?30ma output short-circuit current 45v/? slew rate 20mhz, -3db bandwidth rail-to-rail inputs/outputs logic-controlled, high-voltage switch with adjustable delay timer-delay fault latch for all regulator outputs thermal-overload protection 0.6ma quiescent current max8795a tft-lcd dc-dc converter with operational amplifiers ________________________________________________________________ maxim integrated products 1 ordering information step-up controller gate-on controller switch control gate-off controller ref v cn v cp v main lx fb pgnd agnd drvp fbp v cp v gon v cn v goff del ctl drvn fbn neg4 ref pos4 neg5 pos5 out4 out5 bgnd neg2 pos2 op3 pos3 out2 out3 pos1 out1 neg1 sup com drn src comp in v in max8795a op2 op1 op5 op4 ep minimal operating circuit 19-0793; rev 4; 6/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max8795aetj+ -40 c to +85 c 32 thi n qfn MAX8795AGCJ+ -40 c to +105 c 32 lq fp max8795agtj+ -40 c to +105 c 32 tq fn max8795agtj/v+ -40 c to +105 c 32 tq fn pin configurations appear at end of data sheet. + denotes a lead(pb)-free/rohs-compliant package. /v denotes an automotive-qualified part. evaluation kit available
max8795a tft-lcd dc-dc converter with operational amplifiers 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, ctl to agnd ...................................................-0.3v to +7.5v comp, fb, fbp, fbn, del, ref to agnd .... -0.3v to (v in + 0.3v) pgnd, bgnd to agnd ......................................................0.3v lx to pgnd ............................................................-0.3v to +20v sup to agnd .........................................................-0.3v to +20v drvp to agnd.......................................................-0.3v to +36v pos_, neg_, out_ to agnd ...................-0.3v to (v sup + 0.3v) drvn to agnd ...................................(v in - 30v) to (v in + 0.3v) src to agnd .........................................................-0.3v to +40v com, drn to agnd ................................-0.3v to (v src + 0.3v) drn to com............................................................-30v to +30v pos_ to neg_ rms current ...................................5ma (note 1) out_ maximum continuous output current....................75ma lx switch maximum continuous rms current .....................1.6a continuous power dissipation (t a = +70c) 32-pin thin qfn (derate 34.5mw/c above +70c) 2758mw 32-pin lqfp (derate 48.4mw/c above +70c)....1652.9mw operating temperature range, e grade ............-40c to +85c operating temperature range, g grade .........-40c to +105c junction temperature ......................................................+150c storage temperature range .............................-65c to +150c lead temperature (soldering, 10s) .................................+300c soldering temperature (reflow) .......................................+260c electrical characteristics (v in = 3v, v main = v sup = 14v, v pgnd = v agnd = v bgnd = 0v, i ref = 25a, t a = 0? to +85? . typical values are at t a = +25c, unless otherwise noted.) parameter symbol conditions min typ max units in supply range v in (note 2) 2.5 6.0 v in undervoltage-lockout threshold v uvlo v in rising, typical hysteresis = 50mv 2.05 2.25 2.45 v v fb = v fbp = 1.3v, v fbn = 0v, lx not switching 0.6 1.0 in quiescent current i in v fb = 1.2v, v fbp = 1.4v, v fbn = 0v, lx switching 23 ma duration-to-trigger fault condition fb or fbp below threshold or fbn above threshold 200 ms t a = +25 c to +85 c 1.238 1.250 1.262 ref output voltage no external load t a = 0 c to +85 c 1.232 1.250 1.266 v ref load regulation 0 < i load < 50a 10 mv ref sink current in regulation 10 a ref undervoltage lockout threshold rising edge; typical hysteresis = 160mv 1.15 v temperature rising +160 thermal shutdown hysteresis 15 c main step-up regulator output voltage range v main v in 18 v operating frequency f osc 1000 1200 1400 khz oscillator maximum duty cycle 86 90 93 % t a = +25 c to +85 c 1.221 1.233 1.245 fb regulation voltage v fb no load t a = 0 c to +85 c 1.212 1.233 1.248 v fb fault trip level v fb falling 1.10 1.14 1.17 v fb load regulation 0 < i main < full load, transient only -1 % fb line regulation v in = 2.5v to 6v 0.1 0.4 %/ v fb input bias current v fb = 1.233v +100 +200 na note 1: see figure 2 for the op amp clamp structure.
max8795a tft-lcd dc-dc converter with operational amplifiers _______________________________________________________________________________________ 3 electrical characteristics (continued) (v in = 3v, v main = v sup = 14v, v pgnd = v agnd = v bgnd = 0v, i ref = 25a, t a = 0? to +85? . typical values are at t a = +25c, unless otherwise noted.) parameter symbol conditions min typ max units fb transconductance ? i comp = 2.5a 75 160 280 s fb voltage gain from fb to comp 700 v/ v lx on-resistance r lx ( on ) i lx = 200ma 160 260 m ? lx leakage current i lx v lx = 19v 10 20 a lx current limit i lim v fb = 1.2v, duty cycle = 75% 2.5 3.0 3.5 a current-sense transresistance 0.1 0.2 0.3 v/a soft-start period t ss 14 ms soft-start step size v ref / 128 v operational amplifiers sup supply range v sup 6.0 18.0 v s u p o ver vol tag e faul t thr eshol d 18.0 19 19.9 v sup supply current i sup buffer configuration, v pos _ = v sup / 2, no load 3.5 5.0 ma input offset voltage v os (v neg _, v pos _, v out _) ? v sup / 2 0 12 mv input bias current i bias (v neg _ , v pos _, v out _) ? v sup / 2 -50 0 +50 na input common-mode voltage range v cm 0v sup v common-mode rejection ratio cmrr 0 (v neg _, v pos _) v sup 45 80 db open-loop gain 125 db output voltage swing, high v oh i out _ = 5ma v sup - 100 v sup - 50 mv output voltage swing, low v ol i out _ = -5ma 50 100 mv short-circuit current to v sup / 2, source or sink 75 130 ma power-supply rejection ratio psrr dc, 6v v sup 18v, (v neg _, v pos _) ? v sup / 2 60 db slew rate 45 v/s -3db bandwidth r l = 10k ? , c l = 10pf, buffer configuration 20 mhz gate-on linear-regulator controller fbp regulation voltage v fbp i drvn = 100a 1.231 1.250 1.269 v fbp fault trip level v fbp falling 0.96 1.00 1.04 v fbp input bias current i fbp v fbp = 1.25v -50 +50 na fbp effective load-regulation error (transconductance) v drvp = 10v, i drvp = 50a to 1ma -0.7 -1.5 % fbp line (in) regulation error i drvp = 100a, 2.5v < v in < 6v 1 10 mv drvp sink current i drvp v fbp = 1.1v, v drvp = 10v 1 5 ma drvp off-leakage current v fbp = 1.4v, v drvp = 34v 0.01 10 a soft-start period t ss 14 ms soft-start step size v ref / 128 v
max8795a tft-lcd dc-dc converter with operational amplifiers 4 _______________________________________________________________________________________ electrical characteristics (continued) (v in = 3v, v main = v sup = 14v, v pgnd = v agnd = v bgnd = 0v, i ref = 25a, t a = 0? to +85? . typical values are at t a = +25c, unless otherwise noted.) parameter symbol conditions min typ max units gate-off linear-regulator controller fbn regulation voltage v fbn i drvn = 100a, v ref - v fbn 0.984 1 1.015 v fbn fault trip level v fbn rising 370 420 470 mv fbn input bias current i fbn v fbn = 0.25v -50 +50 na fbn effective load-regulation error (transconductance) v drvn = -10v, i drvn = 50a to 1ma 11 25 mv fbn line (in) regulation error i drvn = 0.1ma, 2.5v < v in < 6v 0.7 5 mv drvn source current i drvn v fbn = 300mv, v drvn = -10v 1 5 ma drvn off-leakage current v fbn = 0v, v drvn = -25v -0.01 -10 a soft-start period t ss 14 ms soft-start step size (v ref - v fbn ) / 128 v positive gate-driver timing and control switches del capacitor charge current during startup, v del = 1v 4 5 6 a del turn-on threshold v th ( del ) 1.19 1.25 1.31 v del discharge switch on-resistance during uvlo, v in = 2.0v 20 ? ctl input low voltage v in = 2.5v to 5.5v 0.6 v ctl input high voltage v in = 2.5v to 5.5v 2 v ctl input leakage current ctl = agnd or in -1 +1 a ctl-to-src propagation delay 100 ns src input voltage range 36 v v del = 1.5v, ctl = in 200 300 src input current i src v del = 1.5v, ctl = agnd 115 200 a s rc - to- c o m s w i tch on- resi stance r src ( on ) v del = 1.5v, ctl = in 5 10 ? d rn - to- c o m s w i tch on- resi stance r drn ( on ) v del = 1.5v, ctl = agnd 30 60 ?
max8795a tft-lcd dc-dc converter with operational amplifiers _______________________________________________________________________________________ 5 parameter symbol conditions min max units in supply range v in (note 2) 2.5 6.0 v in undervoltage-lockout threshold v uvlo v in rising, typical hysteresis = 150mv 2.05 2.45 v v fb = v fbp = 1.3v, v fbn = 0v, lx not switching 1.0 in quiescent current i in v fb = 1.2v, v fbp = 1.4v, v fbn = 0v, lx switching 3 ma ref output voltage no external load 1.218 1.277 v ref undervoltage-lockout threshold rising edge; typical hysteresis = 160mv 1.15 v main step-up regulator output voltage range v main v in 18 v operating frequency f osc 900 1400 khz fb regulation voltage v fb no load 1.198 1.260 v fb line regulation v in = 2.5v to 6v 0.4 %/ v fb transconductance ? i comp = 2.5a 75 280 s lx on-resistance r lx ( on ) i lx = 200ma 260 m ? lx current limit i lim v fb = 1.2v, duty cycle = 75% 2.5 3.5 a operational amplifiers sup supply range v sup 618v sup overvoltage fault threshold 18.0 19.9 v sup supply current i sup buffer configuration, v pos _ = v sup / 2, no load 5ma input offset voltage v os (v neg _, v pos _, i out _) = ? v sup / 2 12 mv input common-mode voltage range v cm 0v sup v output voltage swing, high v oh i out _ = 5ma v sup - 100 mv output voltage swing low v ol i out _ = -5ma 100 source 75 short-circuit current to v sup / 2 sink 75 ma gate-on linear-regulator controller fbp regulation voltage v fbp i drvp = 100a 1.210 1.280 v fbp effective load-regulation error (transconductance) v drvp = 10v, i drvp = 50a to 1ma -1.5 % fbp line (in) regulation error i drvp = 100a, 2.5v < v in < 6v 10 mv drvp sink current i drvp v fbp = 1.1v, v drvp = 10v 1 ma electrical characteristics (v in = 3v, v main = v sup = 14v, v pgnd = v agnd = v bgnd = 0v, i ref = 25a, t a = -40? to +85?, unless otherwise noted.) (note 3)
max8795a tft-lcd dc-dc converter with operational amplifiers 6 _______________________________________________________________________________________ electrical characteristics (continued) (v in = 3v, v main = v sup = 14v, v pgnd = v agnd = v bgnd = 0v, i ref = 25a, t a = -40? to +85?, unless otherwise noted.) (note 3) parameter symbol conditions min max units gate-off linear-regulator controller fbn regulation voltage v fbn i drvn = 100a, v ref - v fbn 0.972 1.022 v fbn effective load-regulation error (transconductance) v drvn = -10v, i drvn = 50a to 1ma 25 mv fbn line (in) regulation error i drvn = 0.1ma, 2.5v < v in < 6v 5 mv drvn source current i drvn v fbn = 300mv, v drvn = -10v 1 ma positive gate-driver timing and control switches del capacitor charge current during startup, v del = 1v 4 6 a del turn-on threshold v th ( del ) 1.19 1.31 v ctl input low voltage v in = 2.5v to 5.5v 0.6 v ctl input high voltage v in = 2.5v to 5.5v 2 v src input voltage range 36 v v del = 1.5v, ctl = in 300 src input current i src v del = 1.5v, ctl = agnd 200 a s rc - to- c o m s w i tch on- resi stance r src ( on ) v del = 1.5v, ctl = in 10 ? d rn - to- c o m s w i tch on- resi stance r drn ( on ) v del = 1.5v, ctl = agnd 60 ? electrical characteristics (v in = 3v, v main = v sup = 14v, v pgnd = v agnd = v bgnd = 0v, i ref = 25a, t a = 0? to +105? . typical values are at t a = +25c, unless otherwise noted.) parameter symbol conditions min typ max units in supply range v in (note 2) 2.5 6.0 v in undervoltage-lockout threshold v uvlo v in rising, typical hysteresis = 50mv 2.05 2.25 2.45 v v fb = v fbp = 1.3v, v fbn = 0v, lx not switching 0.6 1.0 in quiescent current i in v fb = 1.2v, v fbp = 1.4v, v fbn = 0v, lx switching 23 ma duration-to-trigger fault condition v fb or fbp below threshold or fbn above threshold 200 ms t a = +25c to +105c 1.238 1.250 1.262 ref output voltage no external load t a = 0c to +105c 1.232 1.250 1.266 v ref load regulation 0 < i load < 50a 10 mv ref sink current in regulation 10 a ref undervoltage-lockout threshold rising edge, typical hysteresis = 160mv 1.15 v temperature rising +160 thermal shutdown hysteresis 15 c
max8795a tft-lcd dc-dc converter with operational amplifiers _______________________________________________________________________________________ 7 electrical characteristics (continued) (v in = 3v, v main = v sup = 14v, v pgnd = v agnd = v bgnd = 0v, i ref = 25a, t a = 0? to +105? . typical values are at t a = +25c, unless otherwise noted.) parameter symbol conditions min typ max units main step-up regulator output voltage range v main v in 18 v operating frequency f osc 1000 1200 1400 khz oscillator maximum duty cycle 86 90 93 % t a = +25c to +105c 1.221 1.233 1.245 fb regulation voltage v fb no load t a = 0c to +105c 1.212 1.233 1.248 v fb fault trip level v fb falling 1.10 1.14 1.17 v fb load regulation 0 < i main < full load, transient only -1 fb line regulation v in = 2.5v to 6v 0.1 0.4 %/v fb input bias current v fb = 1.233v +100 +200 na fb transconductance ? i comp = 2.5a 75 160 280 s fb voltage gain from fb to comp 700 v/v lx on-resistance r lx ( on ) i lx = 200ma 160 300 m ? lx leakage current i lx v lx = 19v 10 20 a lx current limit i lim v fb = 1.2v, duty cycle = 75% 2.5 3.0 3.5 a current-sense transresistance 0.1 0.2 0.3 v/a soft-start period t ss 14 ms soft-start step size v ref / 128 v operational amplifiers sup supply range v sup 6.0 18.0 sup overvoltage fault threshold 18.0 19 19.9 v sup supply current i sup buffer configuration, v pos_ = v sup / 2, no load 3.5 5.0 ma input offset voltage v os (v neg_ , v pos _, v out_ ) ? v sup / 2 0 12 mv input bias current i bias (v neg_ , v pos_ , v out_ ) ? v sup / 2 -50 0 +50 na input common-mode voltage range v cm 0v sup v common-mode rejection ratio cmrr 0 (v neg_ , v pos_ ) v sup 45 80 db open-loop gain 125 db output voltage swing, high v oh i out_ = 5ma v sup - 100 v sup - 50 mv output voltage swing, low v ol i out_ = -5ma 50 100 mv short-circuit current to v sup / 2, source or sink 75 130 ma power-supply rejection ratio psrr dc, 6v v sup 18v, (v neg_ , v pos_ ) ? v sup / 2 60 db slew rate 45 v/s -3db bandwidth r l = 10k ? , c l = 10pf, buffer configuration 20 mhz
max8795a tft-lcd dc-dc converter with operational amplifiers 8 _______________________________________________________________________________________ electrical characteristics (continued) (v in = 3v, v main = v sup = 14v, v pgnd = v agnd = v bgnd = 0v, i ref = 25a, t a = 0? to +105? . typical values are at t a = +25c, unless otherwise noted.) parameter symbol conditions min typ max units gate-on linear-regulator controller fbp regulation voltage v fbp i drvp = 100a 1.231 1.250 1.269 v fbp fault trip level v fbp falling 0.96 1.00 1.04 v fbp input bias current i fbp v fbp = 1.25v -50 +50 na fbp effective load-regulation error (transconductance) v drvp = 10v, i drvp = 50a to 1ma -0.7 -1.5 % fbp line (in) regulation error i drvp = 100a, 2.5v < v in < 6v 1 10 mv drvp sink current i drvp v fbp = 1.1v, v drvp = 10v 1 5 ma drvp off-leakage current v fbp = 1.4v, v drvp = 34v 0.01 10 a soft-start period t ss 14 ms soft-start step size v ref / 128 v gate-off linear-regulator controller fbn regulation voltage v fbn i drvn = 100a, v ref - v fbn 0.984 1 1.015 v fbn fault trip level v fbn rising 340 420 510 mv fbn input bias current i fbn v fbn = 0.25v -50 +50 na fbn effective load-regulation error (transconductance) v drvn = -10v, i drvn = 50a to 1ma 11 25 mv fbn line (in) regulation error i drvn = 0.1ma, 2.5v < v in < 6v 0.7 5 mv drvn source current i drvn v fbn = 300mv, v drvn = -10v 1 5 ma drvn off-leakage current v fbn = 0v, v drvn = -25v -0.01 -10 a soft-start period t ss 14 ms soft-start step size (v ref - v fbn ) / 128 v positive gate-driver timing and control switches del capacitor charge current during startup, v del = 1v 4 5 6 a del turn-on threshold v th ( del ) 1.19 1.25 1.31 v del discharge switch on-resistance during uvlo, v in = 2.0v 20 ? ctl input low voltage v in = 2.5v to 5.5v 0.6 v ctl input high voltage v in = 2.5v to 5.5v 2 v ctl input leakage current ctl = agnd or in -1 +1 a ctl-to-src propagation delay 100 ns src input voltage range 36 v v del = 1.5v, ctl = in 200 300 src input current i src v del = 1.5v, ctl = agnd 115 200 a s rc - to- c o m s w i tch on- resi stance r src ( on ) v del = 1.5v, ctl = in 5 12 ? d rn- to-c om s w i tch on- resi stance r drn ( on ) v del = 1.5v, ctl = agnd 30 70 ?
max8795a tft-lcd dc-dc converter with operational amplifiers _______________________________________________________________________________________ 9 electrical characteristics (v in = 3v, v main = v sup = 14v, v pgnd = v agnd = v bgnd = 0v, i ref = 25a, t a = -40? to +105? , unless otherwise noted.) (note3) parameter symbol conditions min max units in supply range v in (note 2) 2.5 6.0 v in undervoltage-lockout threshold v uvlo v in rising, typical hysteresis = 150mv 2.05 2.45 v v fb = v fbp = 1.3v, v fbn = 0v, lx not switching 1.0 in quiescent current i in v fb = 1.2v, v fbp = 1.4v, v fbn = 0v, lx switching 3 ma ref output voltage no external load 1.218 1.277 v ref undervoltage-lockout threshold rising edge, typical hysteresis = 160mv 1.15 v main step-up regulator output voltage range v main v in 18 v operating frequency f osc 900 1400 khz fb regulation voltage v fb no load 1.198 1.260 v fb line regulation v in = 2.5v to 6v 0.4 %/ v fb transconductance ? i comp = 2.5a 75 280 s lx on-resistance r lx ( on ) i lx = 200ma 300 m ? lx current limit i lim v fb = 1.2v, duty cycle = 75% 2.5 3.5 a operational amplifiers sup supply range v sup 618v sup overvoltage fault threshold 18.0 19.9 v sup supply current i sup buffer configuration, v pos_ = v sup / 2, no load 5ma input offset voltage v os (v neg_ , v pos_ , v out_ ) ? v sup / 2 12 mv input common-mode voltage range v cm 0v sup v output voltage swing, high v oh i out_ = 5ma v sup - 100 mv output voltage swing, low v ol i out_ = -5ma 100 mv source 75 short-circuit current to v sup / 2 sink 75 ma
max8795a tft-lcd dc-dc converter with operational amplifiers 10 ______________________________________________________________________________________ note 2: for 5.5v < v in < 6.0v, use max8795a for no longer than 1% of ic lifetime. for continuous operation, input voltage should not exceed 5.5v. note 3: specifications to -40c and +105c are guaranteed by design, not production tested. electrical characteristics (continued) (v in = 3v, v main = v sup = 14v, v pgnd = v agnd = v bgnd = 0v, i ref = 25a, t a = -40? to +105? , unless otherwise noted.) (note3) parameter symbol conditions min max units gate-on linear-regulator controller fbp regulation voltage v fbp i drvp = 100a 1.210 1.280 v fbp effective load-regulation error (transconductance) v drvp = 10v, i drvp = 50a to 1ma -1.5 % fbp line (in) regulation error i drvp = 100a, 2.5v < v in < 6v 10 mv drvp sink current i drvp v fbp = 1.1v, v drvp = 10v 1 ma gate-off linear-regulator controller fbn regulation voltage v fbn i drvn = 100a, v ref - v fbn 0.972 1.022 v fbn effective load-regulation error (transconductance) v drvn = -10v, i drvn = 50a to 1ma 25 mv fbn line (in) regulation error i drvn = 0.1ma, 2.5v < v in < 6v 5 mv drvn source current i drvn v fbn = 300mv, v drvn = -10v 1 ma positive gate-driver timing and control switches del capacitor charge current during startup, v del = 1v 4 6 a del turn-on threshold v th ( del ) 1.19 1.31 v ctl input low voltage v in = 2.5v to 5.5v 0.6 v ctl input high voltage v in = 2.5v to 5.5v 2 v src input voltage range 36 v v del = 1.5v, ctl = in 300 src input current i src v del = 1.5v, ctl = agnd 200 a src-to-com switch on-resistance r src ( on ) v del = 1.5v, ctl = in 12 ? drn-to-com switch on-resistance r drn ( on ) v del = 1.5v, ctl = agnd 70 ?
max8795a tft-lcd dc-dc converter with operational amplifiers ______________________________________________________________________________________ 11 10 s/div step-up regulator pulsed load-transient response 13.9v 50ma c max8795a toc05 b 0a a a: load current, 1a/div b: v main , 200mv/div, ac-coupled c: inductor current, 1a/div timer-delayed overload protection max8795a toc06 40ms/div a: v main , 2v/div b: inductor current, 1a/div a b 0a 0u ref voltage load regulation max8795a toc07 load current ( a) ref voltage (v) 40 30 20 10 1.2475 1.2480 1.2485 1.2490 1.2495 1.2500 1.2470 050 gate-on regulator line regulation max8795a toc08 input voltage (v) voltage error (%) 29 28 27 26 -0.6 -0.4 -0.2 0 -0.8 25 30 i pos = 20ma gate-on regulator load regulation max8795a toc09 load current (ma) voltage error (%) 15 10 5 -0.3 -0.1 -0.5 020 i boost = 200ma a 0v b 0v c 0a step-up regulator soft-start (heavy load) max8795a toc04 2ms/div a: v in , 5v/div b: v main , 5v/div c: inductor current, 1a/div step-up efficiency vs. load current max9795a toc01 load current (ma) efficiency (%) 100 10 75 80 85 90 70 1 1000 v in = 5v v main = 13.9v switching frequency vs. input voltage max9795a toc02 input voltage (v) switching frequency (mhz) 5.0 4.5 4.0 3.5 3.0 1.1 1.2 1.3 1.4 1.0 2.5 5.5 step-up supply current vs. supply voltage max8795a toc03 supply voltage (v) supply current (ma) 5.5 5.0 4.5 4.0 3.5 3.0 3 9 6 12 15 18 0 2.5 6.0 no load, sup disconnected, r1 = 221k ? , r2 = 21.5k ? current into inductor current into in pin typical operating characteristics (circuit of figure 1, v in = 5v, v main = 14v, v gon = 25v, v goff = -10v, t a = +25c, unless otherwise noted.)
max8795a tft-lcd dc-dc converter with operational amplifiers 12 ______________________________________________________________________________________ gate-off regulator line regulation max8795a toc10 input voltage (v) voltage error (%) -10 -12 -14 -0.8 -0.4 -0.6 -0.2 0.2 0 0.4 -1.0 -16 i neg = 50ma gate-off regulator load regulation max8795a toc11 load current (ma) voltage error (%) 40 30 20 10 -0.8 -0.6 -0.4 -0.2 0 0.2 -1.0 050 i boost = 0ma 4ms/div power-up sequence 0v max8795a toc12 b 0v a a: v main , 10v/div b: v pos , 20v/div c: v neg , 10v/div d: v com , 20v/div 0v c d 0v sup supply current vs. sup voltage i sup (ma) max8795a toc13 6 8 10 12 16 14 18 2.8 3.1 3.0 2.9 3.3 3.2 3.5 3.4 3.6 v sup (v) 4 s/div operational-amplifier rail-to-rail input/output 0v max8795a toc14 b 0v a a: input signal, 5v/div b: output signal, 5v/div v sup = 15v typical operating characteristics (continued) (circuit of figure 1, v in = 5v, v main = 14v, v gon = 25v, v goff = -10v, t a = +25c, unless otherwise noted.)
max8795a tft-lcd dc-dc converter with operational amplifiers ______________________________________________________________________________________ 13 typical operating characteristics (continued) (circuit of figure 1, v in = 5v, v main = 14v, v gon = 25v, v goff = -10v, t a = +25c, unless otherwise noted.) 400ns/div operational-amplifier load-transient response 0v max8795a toc15 b -50ma a a: output voltage, 1v/div, ac-coupled b: output current, 50ma/div +50ma 0ma 1 s/div operational-amplifier large-signal response 0v max8795a toc16 b a a: input signal, 5v/div b: output signal, 5v/div 0v v sup = 15v 400ns/div operational-amplifier small-signal response 0v max8795a toc17 b a a: input signal, 100mv/div b: output signal, 100mv/div 0v pin name function 1 src switch input. source of the internal high-voltage p-channel mosfet. bypass src to pgnd with a minimum 0.1f capacitor close to the pins. 2 ref reference bypass terminal. bypass ref to agnd with a minimum of 0.22f close to the pins. 3 agnd analog ground for step-up regulator and linear regulators. connect to power ground (pgnd) underneath the ic. 4 pgnd power ground. pgnd is the source of the main step-up n-channel power mosfet. connect pgnd to the output-capacitor ground terminals through a short, wide pcb trace. connect to analog ground (agnd) underneath the ic. 5 out1 operational-amplifier 1 output 6 neg1 operational-amplifier 1 inverting input 7 pos1 operational-amplifier 1 noninverting input 8 out2 operational-amplifier 2 output 9 neg2 operational-amplifier 2 inverting input 10 pos2 operational-amplifier 2 noninverting input 11 bgnd analog ground for operational amplifiers. connect to power ground (pgnd) underneath the ic. 12 pos3 operational-amplifier 3 noninverting input 13 out3 operational-amplifier 3 output 14 sup operational-amplifier power input. positive supply rail for the operational amplifiers. typically connected to v main . bypass sup to bgnd with a 0.1f capacitor. 15 pos4 operational-amplifier 4 noninverting input 16 neg4 operational-amplifier 4 inverting input pin description
max8795a tft-lcd dc-dc converter with operational amplifiers 14 ______________________________________________________________________________________ pin description (continued) pin name function 17 out4 operational-amplifier 4 output 18 pos5 operational-amplifier 5 noninverting input 19 neg5 operational-amplifier 5 inverting input 20 out5 operational-amplifier 5 output 21 lx n-channel power mosfet drain and switching node. connect the inductor and schottky diode to lx and minimize the trace area for lowest emi. 22 in supply voltage input. in can range from 2.5v to 6v. 23 fb step-up regulator feedback input. regulates to 1.233v (nominal). connect a resistive voltage-divider from the output (v main ) to fb to analog ground (agnd). place the divider within 5mm of fb. 24 comp step-up regulator error-amplifier compensation point. connect a series rc from comp to agnd. see the loop compensation section for component selection guidelines. 25 fbp gate-on linear-regulator feedback input. fbp regulates to 1.25v (nominal). connect fbp to the center of a resistive voltage-divider between the regulator output and agnd to set the gate-on linear- regulator output voltage. place the resistive voltage-divider within 5mm of fbp. 26 drvp gate-on linear-regulator base drive. open drain of an internal n-channel mosfet. connect drvp to the base of an external pnp pass transistor. see the pass-transistor selection section. 27 fbn gate-off linear-regulator feedback input. fbn regulates to 250mv (nominal). connect fbn to the center of a resistive voltage-divider between the regulator output and ref to set the gate-off linear- regulator output voltage. place the resistive voltage-divider within 5mm of fbn. 28 drvn gate-off linear-regulator base drive. open drain of an internal p-channel mosfet. connect drvn to the base of an external npn pass transistor. see the pass-transistor selection section. 29 del high-voltage switch delay input. connect a capacitor from del to agnd to set the high-voltage switch startup delay. 30 ctl high-voltage switch control input. when ctl is high, the high-voltage switch between com and src is on and the high-voltage switch between com and drn is off. when ctl is low, the high-voltage switch between com and src is off and the high-voltage switch between com and drn is on. ctl is inhibited by the undervoltage lockout or when the voltage on del is less than 1.25v. 31 drn switch input. drain of the internal high-voltage back-to-back p-channel mosfets connected to com. 32 com internal high-voltage mosfet switch common terminal. do not allow the voltage on com to exceed v src . ep exposed paddle. must be connected to agnd. do not use as the only ground connection.
max8795a tft-lcd dc-dc converter with operational amplifiers ______________________________________________________________________________________ 15 typical operating circuit the max8795a typical operating circuit (figure 1) is a complete power-supply system for tft lcds. the circuit generates a +14v source-driver supply and +25v and -10v gate-driver supplies. the input voltage range for the ic is from +2.5v to +5.5v. the listed load currents in figure 1 are available from a +4.5v to +5.5v supply. table 1 lists some recommended components, and table 2 lists the contact information of component suppliers. c3 0.1 f c4 0.1 f c14 68pf c11 0.1 f lx d1 l1 3.0 h lx c2 22 f d2 v main 14v/500ma r1 137k ? 1% r2 13.3k ? 1% r3 6.8k ? r6 1k ? r19 100k ? r20 100k ? r17 100k ? r18 100k ? r15 100k ? r16 100k ? r13 100k ? r14 100k ? r11 100k ? r12 100k ? r4 191k ? 1% r5 10.0k ? 1% q1 c5 0.47 f v gon 25v/20ma c6 0.1 f lx v in 4.5v to 5.5v d3 q2 c1 22 f c12 220 f c13 0.1 f r10 10 ? 180k ? r9 6.8k ? c10 0.1 f r7 324k ? 1% r8 31.6k ? 1% c9 0.22 f c8 0.22 f v goff -10v/50ma c7 0.033 f to vcom backplane in comp drvn fbn ref fb agnd pgnd drvp fbp src com lx del neg1 neg2 out2 out3 neg4 out4 neg5 out5 out1 drn ctl sup bgnd pos1 pos2 pos3 pos4 pos5 max8795a ep figure 1. typical operating circuit designation description c1 22f, 6.3v x5r ceramic capacitor (1210) tdk c3225x5r0j227m c2 22f, 16v x5r ceramic capacitor (1812) tdk c4532x5x1c226m d1 3a, 30v schottky diode (m-flat) toshiba cms02 d2, d3 200ma, 100v, dual ultra-fast diodes (sot23) fairchild mmbd4148se designation description l1 3.0h, 3a inductor sumida cdrh6d28-3r0 q1 200ma, 40v pnp bipolar transistor (sot23) fairchild mmbt3906 q2 200ma, 40v npn bipolar transistor (sot23) fairchild mmbt3904 table 1. component list
max8795a tft-lcd dc-dc converter with operational amplifiers 16 ______________________________________________________________________________________ supplier phone fax website fairchild 408-822-2000 408-822-2102 www.fairchildsemi.com sumida 847-545-6700 847-545-6720 www.sumida.com tdk 847-803-6100 847-390-4405 www.component.tdk.com toshiba 949-455-2000 949-859-3963 www.toshiba.com/taec table 2. component suppliers detailed description the max8795a contains a high-performance step-up switching regulator, two low-cost linear-regulator con- trollers, multiple high-current operational amplifiers, and startup timing and level-shifting functionality useful for active-matrix tft lcds. figure 2 shows the max8795a functional diagram. main step-up regulator the main step-up regulator employs a current-mode, fixed-frequency pwm architecture to maximize loop bandwidth and provide fast transient response to pulsed loads typical of tft-lcd panel source drivers. the 1.2mhz switching frequency allows the use of low- profile inductors and ceramic capacitors to minimize the thickness of lcd panel designs. the integrated high-efficiency mosfet and the ics built-in digital soft-start functions reduce the number of external com- ponents required while controlling inrush currents. the output voltage can be set from v in to 18v with an exter- nal resistive voltage-divider. the regulator controls the output voltage and the power delivered to the output by modulating the duty cycle (d) of the internal power mosfet in each switching cycle. the duty cycle of the mosfet is approximated by: figure 3 shows the functional diagram of the step-up regulator. an error amplifier compares the signal at fb to 1.233v and changes the comp output. the voltage at comp sets the peak inductor current. as the load varies, the error amplifier sources or sinks current to the comp output accordingly to produce the inductor peak current necessary to service the load. to maintain sta- bility at high duty cycles, a slope-compensation signal is summed with the current-sense signal. on the rising edge of the internal clock, the controller sets a flip-flop, turning on the n-channel mosfet and applying the input voltage across the inductor. the current through the inductor ramps up linearly, storing energy in its magnetic field. once the sum of the current-feedback signal and the slope compensation exceeds the comp d vv v main in main ? step-up controller gate-on controller switch control gate-off controller ref v cn v cp v main lx fb pgnd agnd drvp fbp v cp v gon v cn v goff del ctl drvn fbn neg4 ref pos4 neg5 pos5 out4 out5 bgnd neg2 pos2 op3 pos3 out2 out3 pos1 out1 neg1 sup com drn src comp in v in max8795a op2 op1 op5 op4 ep figure 2. max8795a functional diagram
max8795a tft-lcd dc-dc converter with operational amplifiers ______________________________________________________________________________________ 17 q r s reset dominant current sense oscillator slope comp clock lx pgnd fb comp 1.233v 1.14v soft- start v limit pwm comparator fault comparator ilim comparator to fault latch error amp figure 3. step-up regulator functional diagram voltage, the controller resets the flip-flop and turns off the mosfet. since the inductor current is continuous, a transverse potential develops across the inductor that turns on the diode (d1). the voltage across the induc- tor then becomes the difference between the output voltage and the input voltage. this discharge condition forces the current through the inductor to ramp back down, transferring the energy stored in the magnetic field to the output capacitor and the load. the mosfet remains off for the rest of the clock cycle. gate-on linear-regulator controller, reg p the gate-on linear-regulator controller (reg p) is an analog gain block with an open-drain n-channel output. it drives an external pnp pass transistor with a 6.8k ? base-to-emitter resistor (figure 1). its guaranteed base- drive sink current is at least 1ma. the regulator including q1 in figure 1 uses a 0.47f ceramic output capacitor and is designed to deliver 20ma at 25v. other output voltages and currents are possible with the proper pass transistor and output capacitor. see the pass-transistor selection and stability requirements sections. reg p is typically used to provide the tft-lcd gate drivers gate-on voltage. use a charge pump with as many stages as necessary to obtain a voltage exceed- ing the required gate-on voltage (see the selecting the number of charge-pump stages section). note the voltage rating of drvp is 36v. if the charge-pump out- put voltage can exceed 36v, an external cascode npn transistor should be added as shown in figure 4. alternately, the linear regulator can control an interme- diate charge-pump stage while regulating the final charge-pump output (figure 5). max8795a drvp fbp v main from charge-pump output npn cascode transistor pnp pass transistor v gon figure 4. using cascoded npn for charge-pump output voltages > 36v max8795a drvp fbp v gon 35v lx v main 14v 0.22 f 0.1 f 0.1 f 0.47 f 47pf 150pf 274k ? 1% 10.2k ? 1% 6.8k ? 68pf q1 figure 5. the linear regulator controls the intermediate charge- pump stage.
max8795a tft-lcd dc-dc converter with operational amplifiers 18 ______________________________________________________________________________________ reg p is enabled after the ref voltage exceeds 1.0v. each time it is enabled, the controller goes through a soft-start routine that ramps up its internal reference dac in 128 steps. gate-off linear-regulator controller, reg n the gate-off linear-regulator controller (reg n) is an analog gain block with an open-drain p-channel output. it drives an external npn pass transistor with a 6.8k ? base-to-emitter resistor (figure 1). its guaranteed base- drive source current is at least 1ma. the regulator including q2 in figure 1 uses a 0.47f ceramic output capacitor and is designed to deliver 50ma at -10v. other output voltages and currents are possible with the proper pass transistor and output capacitor (see the pass- transistor selection and stability requirements sections). reg n is typically used to provide the tft-lcd gate drivers gate-off voltage. a negative voltage can be produced using a charge-pump circuit as shown in figure 1. reg n is enabled after the voltage on ref exceeds 1.0v. each time it is enabled, the control goes through a soft-start routine that ramps down its internal reference dac from v ref to 250mv in 128 steps. operational amplifiers the max8795a has five operational amplifiers. the opera- tional amplifiers are typically used to drive the lcd back- plane (vcom) or the gamma-correction divider string. they feature 130ma output short-circuit current, 45v/s slew rate, and 20mhz/3db bandwidth. the rail-to-rail input and output capability maximizes system flexibility. short-circuit current limit and input clamp the operational amplifiers limit short-circuit current to approximately 130ma if the output is directly shorted to sup or to bgnd. if the short-circuit condition persists, the junction temperature of the ic rises until it reaches the thermal-shutdown threshold (+160 c typ). once the junc- tion temperature reaches the thermal-shutdown threshold, an internal thermal sensor immediately sets the thermal fault latch, shutting off all the ics outputs. the device remains inactive until the input voltage is cycled. the operational amplifiers have 4v input clamp structures in series with a 500 ? resistance and a diode (figure 2). driving pure capacitive load the operational amplifiers are typically used to drive the lcd backplane (vcom) or the gamma-correction divider string. the lcd backplane consists of a distrib- uted series capacitance and resistance, a load that can be easily driven by the operational amplifier. however, if the operational amplifier is used in an application with a pure capacitive load, steps must be taken to ensure stable operation. as the operational amplifiers capacitive load increases, the amplifiers bandwidth decreases and gain peaking increases. a 5 ? to 50 ? small resistor placed between out_ and the capacitive load reduces peaking, but also reduces the gain. an alternative method of reducing peaking is to place a series rc network (snubber) in par- allel with the capacitive load. the rc network does not continuously load the output or reduce the gain. typical values of the resistor are between 100 ? and 200 ? , and the typical value of the capacitor is 10nf. undervoltage lockout (uvlo) the uvlo circuit compares the input voltage at in with the uvlo threshold (2.25v rising, 2.20v falling, typ) to ensure the input voltage is high enough for reliable operation. the 50mv (typ) hysteresis prevents supply transients from causing a restart. once the input voltage exceeds the uvlo rising threshold, startup begins. when the input volt- age falls below the uvlo falling threshold, the controller turns off the main step-up regulator, turns off the linear- regulator outputs, and disables the switch control block; the operational-amplifier outputs are high impedance. reference voltage (ref) the reference output is nominally 1.25v and can source at least 50a (see the typical operating characteristics ). bypass ref with a 0.22f ceramic capacitor connected between ref and agnd. power-up sequence and soft-start once the voltage on in exceeds approximately 2.25v, the reference turns on. with a 0.22f ref bypass capacitor, the reference reaches its regulation voltage of 1.25v in approximately 1ms. when the reference voltage exceeds 1.0v, the ic enables the main step-up regulator, the gate- on linear-regulator controller, and the gate-off linear-regu- lator controller simultaneously. the ic employs soft-start for each regulator to minimize inrush current and voltage overshoot and to ensure a well- defined startup behavior. each output uses a 7-bit soft-start dac. for the step-up and the gate-on linear regulator, the dac output is stepped in 128 steps from zero up to the ref- erence voltage. for the gate-off linear regulator, the dac output steps from the reference down to 250mv in 128 steps from zero up to the reference voltage. for the gate- off linear regulators voltage ramp soft-start, the dac output steps from the reference down to 250mv in 128 steps. the soft-start duration is 14ms (typ) for all three regulators, and del remains pulled down to agnd during the soft start period. once the main step-up regulator, the gate-on linear-regula- tor controller, and the gate-off linear-regulator controller reach regulation, a 5a current source starts charging
max8795a tft-lcd dc-dc converter with operational amplifiers ______________________________________________________________________________________ 19 c del . once the c del capacitor voltage exceeds 1.25v (typ), the switch-control block is and op amps are enabled as shown in figure 6. after the switch-control block is enabled, com can be connected to src or drn through the internal p-channel switches, depending upon the state of ctl. before startup and when in is less than v uvlo , del is internally connected to agnd to discharge c del . select c del to set the initial start-up delay and the switch-control block startup delay times using the following equation: switch-control block the switch-control input (ctl) is not activated until all four of the following conditions are satisfied: the input voltage exceeds v uvlo , the soft-start routine of all the regulators is complete, there is no fault condition detect- ed, and v del exceeds its turn-on threshold. once acti- vated and if ctl is high, the 5 ? internal p-channel switch (q1) between com and src turns on and the cdelaytime ia v del = _ . 6 125 2.25v 1.05v input voltage ok soft- start begins soft- start ends switch control enabled 12ms v in v ref v main v gon v goff 1.25v v del figure 6. power-up sequence max8795a fb ok fbp ok fbn ok 2.25v 5 a ref drn com src q1 q2 ctl del in figure 7. switch-control block
max8795a tft-lcd dc-dc converter with operational amplifiers 20 ______________________________________________________________________________________ 30 ? p-channel switch (q2) between drn and com turns off. if ctl is low, q1 turns off and q2 turns on. fault protection during steady-state operation, if the output of the main regulator or any of the linear-regulator outputs does not exceed its respective fault-detection threshold, the max8795a activates an internal fault timer. if any condi- tion or combination of conditions indicates a continuous fault for the fault-timer duration (200ms typ), the max8795a sets the fault latch to shut down all the outputs except the reference. once the fault condition is removed, cycle the input voltage (below the uvlo falling threshold) to clear the fault latch and reactivate the device. the fault- detection circuit is disabled during the soft-start time. thermal-overload protection thermal-overload protection prevents excessive power dis- sipation from overheating the max8795a. when the junc- tion temperature exceeds +160 c, a thermal sensor immediately activates the fault protection, which shuts down all outputs except the reference, allowing the device to cool down. once the device cools down by approximate- ly 15 c, cycle the input voltage (below the uvlo falling threshold) to clear the fault latch and reactivate the device. the thermal-overload protection protects the controller in the event of fault conditions. for continuous opera- tion, do not exceed the absolute maximum junction temperature rating of +150 c. design procedure main step-up regulator inductor selection the minimum inductance value, peak current rating, and series resistance are factors to consider when selecting the inductor. these factors influence the con- verters efficiency, maximum output load capability, transient-response time, and output voltage ripple. size and cost are also important factors to consider. the maximum output current, input voltage, output volt- age, and switching frequency determine the inductor value. very high inductance values minimize the current ripple, and therefore, reduce the peak current, which decreases core losses in the inductor and conduction losses in the entire power path. however, large inductor values also require more energy storage and more turns of wire, which increase size and can increase conduction losses in the inductor. low inductance values decrease the size, but increase the current ripple and peak current. finding the best inductor involves choosing the best com- promise between circuit efficiency, inductor size, and cost. the equations used here include a constant lir, which is the ratio of the inductor peak-to-peak ripple current to the average dc inductor current at the full load current. the best trade-off between inductor size and circuit efficiency for step-up regulators generally has an lir between 0.3 and 0.6. however, depending on the ac characteristics of the inductor core material and ratio of inductor resistance to other power-path resistances, the best lir can shift up or down. if the inductor resistance is relatively high, more ripple can be accepted to reduce the number of turns required and increase the wire diameter. if the inductor resistance is relatively low, increasing inductance to lower the peak current can decrease losses throughout the power path. if extremely thin high-resistance inductors are used, as is common for lcd-panel applications, the best lir can increase to between 0.5 and 1.0. once a physical inductor is chosen, higher and lower values of the inductor should be evaluated for efficien- cy improvements in typical operating regions. calculate the approximate inductor value using the typ- ical input voltage (v in ), the maximum output current (i main(max) ), the expected efficiency ( typ ) taken from an appropriate curve in the typical operating characteristics section, and an estimate of lir based on the above discussion: choose an available inductor value from an appropriate inductor family. calculate the maximum dc input cur- rent at the minimum input voltage (v in(min) ) using con- servation of energy and the expected efficiency at that operating point ( min ) taken from the appropriate curve in the typical operating characteristics : calculate the ripple current at that operating point and the peak current required for the inductor: the inductors saturation current rating and the max8795as lx current limit (i lim ) should exceed i peak , and the inductors dc current rating should exceed i in(dc,max) . for good efficiency, choose an inductor with less than 0.1 ? series resistance. considering the typical operating circuit, the maximum load current (i main(max) ) is 500ma with a 14v output and i vvv lv f ii i ripple in min main in min main osc peak in dcmax ripple = ? =+ () () (, ) () 2 i iv v in dcmax main max main in min min (, ) () () = l v v vv i f lir in main main in main max osc typ = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 ()
max8795a tft-lcd dc-dc converter with operational amplifiers ______________________________________________________________________________________ 21 a typical input voltage of 5v. choosing an lir of 0.5 and estimating efficiency of 85% at this operating point: using the circuits minimum input voltage (4.5v) and estimating efficiency of 80% at that operating point: the ripple current and the peak current are: output-capacitor selection the total output voltage ripple has two components: the capacitive ripple caused by the charging and discharging of the output capacitance, and the ohmic ripple due to the capacitors equivalent series resistance (esr): where i ripple is the ripple inductor current (see the inductor selection section). for ceramic capacitors, the output voltage ripple is typically dominated by v ripple(c) . the voltage rating and temperature charac- teristics of the output capacitor must also be considered. input-capacitor selection the input capacitor (c in ) reduces the current peaks drawn from the input supply and reduces noise injection into the ic. a 22f ceramic capacitor is used in the typi- cal applications circuit (figure 1) because of the high source impedance seen in typical lab setups. actual applications usually have much lower source impedance since the step-up regulator often runs directly from the output of another regulated supply. typically, c in can be reduced below the values used in the typical applica- tions circuit. ensure a low-noise supply at in by using adequate c in . alternately, greater voltage variation can be tolerated on c in if in is decoupled from c in using an rc lowpass filter (see r10 and c13 in figure 1). rectifier diode the max8795as high switching frequency demands a high-speed rectifier. schottky diodes are recommended for most applications because of their fast recovery time and low forward voltage. in general, a 2a schottky diode complements the internal mosfet well. output-voltage selection the output voltage of the main step-up regulator can be adjusted by connecting a resistive voltage-divider from the output (v main ) to agnd with the center tap connected to fb (see figure 1). select r2 in the 10k ? to 50k ? range. calculate r1 with the following equation: where v fb , the step-up regulators feedback set point, is 1.233v. place r1 and r2 close to the ic. loop compensation choose r comp to set the high-frequency integrator gain for fast transient response. choose c comp to set the integrator zero to maintain loop stability. for low-esr output capacitors, use the following equa- tions to obtain stable performance and good transient response: to further optimize transient response, vary r comp in 20% steps and c comp in 50% steps while observing transient-response waveforms. charge pumps selecting the number of charge-pump stages for highest efficiency, always choose the lowest num- ber of charge-pump stages that meet the output requirement. figures 8 and 9 show the positive and negative charge-pump output voltages for a given v main for one-, two-, and three-stage charge pumps. r vv c li c vc ir comp in out out main max comp out out main max comp 253 10 () () rr v v main fb 12 1 = ? ? ? ? ? ? ? : () ( ) () () ( ) vv v v i c vv vf and vir ripple ripple c ripple esr ripple c main out main in main osc ripple esr peak esr cout =+ ? ? ? ? ? ? ? i vvv h v mhz a ia a a ripple peak = ? ? =+ 45 14 45 33 14 12 077 194 077 2 233 .( .) .. . . . . i av v a in dcmax (, ) . .. . = 05 14 45 08 194 l v v vv a mhz h = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 5 14 14 5 05 12 085 05 33 2 .. . . .
max8795a tft-lcd dc-dc converter with operational amplifiers 22 ______________________________________________________________________________________ the number of positive charge-pump stages is given by: where n pos is the number of positive charge-pump stages, v gon is the gate-on linear-regulator reg p out- put, v main is the main step-up regulator output, v d is the forward-voltage drop of the charge-pump diode, and v dropout is the dropout margin for the linear reg- ulator. use v dropout = 0.3v. the number of negative charge-pump stages is given by: where n neg is the number of negative charge-pump stages, v goff is the gate-off linear-regulator reg n output, v main is the main step-up regulator output, v d is the forward-voltage drop of the charge-pump diode, and v dropout is the dropout margin for the linear reg- ulator. use v dropout = 0.3v. the above equations are derived based on the assumption that the first stage of the positive charge pump is connected to v main and the first stage of the negative charge pump is connected to ground. sometimes fractional stages are more desirable for bet- ter efficiency. this can be done by connecting the first stage to v in or another available supply. if the first charge-pump stage is powered from v in , the above equations become: flying capacitors increasing the flying-capacitor (c x ) value lowers the effective source impedance and increases the output- current capability. increasing the capacitance indefinitely has a negligible effect on output-current capability because the internal switch resistance and the diode impedance place a lower limit on the source imped- ance. a 0.1f ceramic capacitor works well in most low-current applications. the flying capacitors voltage rating must exceed the following: where n is the stage number in which the flying capaci- tor appears, and v main is the output voltage of the main step-up regulator. vnv cx main > n vv v vv n vv v vv pos gon dropout in main d neg goff dropout in main d = ++ ? = ?+ + ? 2 2 n vv vv neg goff dropout main d = ?+ ? 2 n vv v vv pos gon dropout main main d = +? ? 2 positive charge-pump output voltage vs. v main v main (v) g_on (v) 12 10 8 6 4 10 20 30 40 50 60 0 214 2-stage charge pump 3-stage charge pump v d = 0.3v to 1v 1-stage charge pump figure 8. positive charge-pump output voltage vs. v main negative charge-pump output voltage vs. v main v main (v) g_off (v) 12 10 8 6 4 -40 -35 -30 -25 -20 -15 -10 -5 -0 -45 214 1-stage charge pump 2-stage charge pump 3-stage charge pump v d = 0.3v to 1v figure 9. negative charge-pump output voltage vs. v main
max8795a tft-lcd dc-dc converter with operational amplifiers ______________________________________________________________________________________ 23 charge-pump output capacitor increasing the output capacitance or decreasing the esr reduces the output ripple voltage and the peak-to- peak transient voltage. with ceramic capacitors, the output voltage ripple is dominated by the capacitance value. use the following equation to approximate the required capacitor value: where c out_cp is the output capacitor of the charge pump, i load_cp is the load current of the charge pump, and v ripple_cp is the peak-to-peak value of the output ripple. charge-pump rectifier diodes use low-cost silicon switching diodes with a current rat- ing equal to or greater than two times the average charge-pump input current. if it helps avoid an extra stage, some or all of the diodes can be replaced with schottky diodes with an equivalent current rating. linear-regulator controllers output-voltage selection adjust the gate-on linear-regulator (reg p) output volt- age by connecting a resistive voltage-divider from the reg p output to agnd with the center tap connected to fbp (figure 1). select the lower resistor of the divider r5 in the range of 10k ? to 30k ? . calculate the upper resistor r4 with the following equation: where v fbp = 1.25v (typ). adjust the gate-off linear-regulator reg n output volt- age by connecting a resistive voltage-divider from v goff to ref with the center tap connected to fbn (figure 1). select r8 in the 20k ? to 50k ? range. calculate r7 with the following equation: where v fbn = 250mv, v ref = 1.25v. note that ref can only source up to 50a; using a resistor less than 20k ? for r8 results in higher bias current than ref can supply. pass-transistor selection the pass transistor must meet specifications for current gain (h fe ), input capacitance, collector-emitter saturation voltage, and power dissipation. the transistors current gain limits the guaranteed maximum output current to: where i drv is the minimum guaranteed base-drive cur- rent, v be is the transistors base-to-emitter forward volt- age drop, and r be is the pullup resistor connected between the transistors base and emitter. furthermore, the transistors current gain increases the linear regula- tors dc loop gain (see the stability requirements sec- tion), so excessive gain destabilizes the output. therefore, transistors with current gain over 100 at the maximum output current can be difficult to stabilize and are not recommended unless the high gain is needed to meet the load-current requirements. the transistors saturation voltage at the maximum out- put current determines the minimum input-to-output voltage differential that the linear regulator can support. also, the packages power dissipation limits the usable maximum input-to-output voltage differential. the maxi- mum power-dissipation capability of the transistors package and mounting must exceed the actual power dissipated in the device. the power dissipated equals the maximum load current (i load(max)_lr ) multiplied by the maximum input-to-output voltage differential: where v in(max)_lr is the maximum input voltage of the linear regulator, and v out _ lr is the output voltage of the linear regulator. stability requirements the max8795a linear-regulator controllers use an inter- nal transconductance amplifier to drive an external pass transistor. the transconductance amplifier, the pass transistor, the base-emitter resistor, and the out- put capacitor determine the loop stability. the following applies to both linear-regulator controllers in the max8795a. the transconductance amplifier regulates the output voltage by controlling the pass transistors base cur- rent. the total dc loop gain is approximately: where v t is 26mv at room temperature, and i bias is the current through the base-to-emitter resistor (r be ). for the max8795a, the bias currents for both the gate-on a v ih i v vlr t bias fe load lr ref _ _ ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? 10 1 pi v v load max lr in max lr out lr =? ()_ ()_ _ () ii v r h load max drv be be fe min () () =? ? ? ? ? ? ? rr vv vv fbn goff ref fbn 78 = ? ? rr v v gon fbp 45 1 = ? ? ? ? ? ? ? c i fv out cp load cp osc ripple cp _ _ _ 2
max8795a tft-lcd dc-dc converter with operational amplifiers 24 ______________________________________________________________________________________ and gate-off linear-regulator controllers are 0.1ma. therefore, the base-to-emitter resistor for both linear regulators should be chosen to set 0.1ma bias current: the output capacitor and the load resistance create the dominant pole in the system. however, the internal amplifier delay, pass transistors input capacitance, and the stray capacitance at the feedback node create additional poles in the system, and the output capaci- tors esr generates a zero. for proper operation, use the following equations to verify the linear regulator is properly compensated: 1) first, determine the dominant pole set by the linear regulators output capacitor and the load resistor: the unity-gain crossover of the linear regulator is: f crossover = a v_lr f pole_lr 2) the pole created by the internal amplifier delay is approximately 1mhz: f pole_amp = 1mhz 3) next, calculate the pole set by the transistors input capacitance, the transistors input resistance, and the base-to-emitter pullup resistor: g m is the transconductance of the pass transistor, and f t is the transition frequency. both parameters can be found in the transistors data sheet. because rbe is much greater than rin, the above equation can be simplified: substituting for cin and rin yields: 4) next, calculate the pole set by the linear regulators feedback resistance and the capacitance between fb_ and agnd (including stray capacitance): where cfb is the capacitance between fb_ and agnd, r upper is the upper resistor of the linear regu- lators feedback divider, and r lower is the lower resis- tor of the divider. 5) next, calculate the zero caused by the output capacitors esr: where resr is the equivalent series resistance of cout_lr. to ensure stability, choose c out_lr large enough so the crossover occurs well before the poles and zero calculated in steps 2 to 5. the poles in steps 3 and 4 generally occur at several megahertz, and using ceramic capacitors ensures the esr zero occurs at several megahertz as well. placing the crossover below 500khz is sufficient to avoid the amplifier-delay pole and generally works well, unless unusual component choices or extra capacitances move one of the other poles or the zero below 1mhz. applications information power dissipation an ics maximum power dissipation depends on the thermal resistance from the die to the ambient environ- ment and the ambient temperature. the thermal resis- tance depends on the ic package, pcb copper area, other thermal mass, and airflow. the max8795a, with its exposed backside paddle sol- dered to 1in 2 of pcb copper and a large internal ground plane layer, can dissipate approximately 2.76w into +70 c still air. more pcb copper, cooler ambient air, and more airflow increase the possible dissipation, while less copper or warmer air decreases the ics dissipation capability. the major components of power dissipation are the power dissipated in the step-up regulator and the power dissipated by the operational amplifiers. f cr pole esr out lr esr _ _ = 1 2 f cr r pole fb fb upper lower _ (|| ) = 1 2 f f h pole in t fe _ = f cr pole in in in _ = 1 2 : where c g f in m = 2 t in fe m r h g , = f crr pole in in be in _ (||) = 1 2 f i cv pole lr load max lr out lr out lr _ ()_ __ = 2 r v ma v ma k be be == 01 07 01 68 . . . . ?
max8795a tft-lcd dc-dc converter with operational amplifiers ______________________________________________________________________________________ 25 step-up regulator the largest portions of power dissipation in the step-up regulator are the internal mosfet, the inductor, and the output diode. if the step-up regulator has 90% efficiency, approximately 3% to 5% of the power is lost in the internal mosfet, approximately 3% to 4% in the inductor, and approximately 1% in the output diode. the remaining 1% to 3% is distributed among the input and output capacitors and the pcb traces. if the input power is about 5w, the power lost in the internal mosfet is approximately 150mw to 250mw. operational amplifier the power dissipated in the operational amplifiers depends on their output current, the output voltage, and the supply voltage: where i out_(source) is the output current sourced by the operational amplifier, and i out_(sink) is the output current that the operational amplifier sinks. in a typical case where the supply voltage is 13v and the output voltage is 6v with an output source current of 30ma, the power dissipated is 180mw. pcb layout and grounding careful pcb layout is important for proper operation. use the following guidelines for good pcb layout: ? minimize the area of high-current loops by placing the inductor, the output diode, and the output capacitors near the input capacitors and near the lx and pgnd pins. the high-current input loop goes from the positive terminal of the input capacitor to the inductor, to the ics lx pin, out of pgnd, and to the input capacitors negative terminal. the high- current output loop is from the positive terminal of the input capacitor to the inductor, to the output diode (d1), and to the positive terminal of the output capacitors, reconnecting between the output capac- itor and input capacitor ground terminals. connect these loop components with short, wide connec- tions. avoid using vias in the high-current paths. if vias are unavoidable, use many vias in parallel to reduce resistance and inductance. ? create a power-ground island (pgnd) consisting of the input and output capacitor grounds, pgnd pin, and any charge-pump components. connect all of these together with short, wide traces or a small ground plane. maximizing the width of the power- ground traces improves efficiency and reduces out- put voltage ripple and noise spikes. create an analog ground plane (agnd) consisting of the agnd pin, all the feedback-divider ground connec- tions, the operational-amplifier divider ground con- nections, the comp and del capacitor ground connections, and the devices exposed backside paddle. connect the agnd and pgnd islands by connecting the pgnd pin directly to the exposed backside paddle. make no other connections between these separate ground planes. ? place all feedback voltage-divider resistors within 5mm of their respective feedback pins. the dividers center trace should be kept short. placing the resis- tors far away causes their fb traces to become antennas that can pick up switching noise. take care to avoid running any feedback trace near lx or the switching nodes in the charge pumps, or pro- vide a ground shield. ? place the in pin and ref pin bypass capacitors as close as possible to the device. the ground connec- tion of the in bypass capacitor should be connected directly to the agnd pin with a wide trace. ? minimize the length and maximize the width of the traces between the output capacitors and the load for best transient responses. ? minimize the size of the lx node while keeping it wide and short. keep the lx node away from feed- back nodes (fb, fbp, and fbn) and analog ground. use dc traces to shield if necessary. refer to the max8795a evaluation kit for an example of proper pcb layout. pd i v v pd i v source out source sup out sink out sink out =? = _( ) _ _( ) _ () chip information transistor count: 6595 process: bicmos
max8795a tft-lcd dc-dc converter with operational amplifiers 26 ______________________________________________________________________________________ pin configurations 32 com max8795a thin qfn 5mm x 5mm 28 drvn 27 fbn 26 drvp 25 fbp 29 del 30 ctl 31 drn 20 out5 19 neg5 18 pos5 17 out4 21 lx 22 in 23 fb 24 comp 12 pos3 11 bgnd 10 pos2 9 neg2 13 out3 14 sup 15 pos4 16 neg4 5 out1 6 neg1 7 pos1 8 out2 4 pgnd 3 agnd 2 ref 1 src top view max8795a lqfp 7mm x 7mm + top view 29 30 28 27 12 11 13 ref pgnd out1 neg1 pos1 14 src fb lx out5 co m p neg5 pos5 12 drvn 4567 23 24 22 20 19 18 del ctl sup out3 pos3 bgnd agnd in 3 21 31 10 drn pos2 32 9 co m neg2 fbn 26 15 pos4 drvp 25 16 neg4 out2 out4 8 17 fbp
max8795a tft-lcd dc-dc converter with operational amplifiers ______________________________________________________________________________________ 27 package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a "+", "#", or "-" in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per - tains to the package regardless of rohs status. qfn thin.eps package type package code outline no. land pattern no. 32 tqfn t3255+3 21-0140 90-0025 32 lqfp c32+2 21-0054 90-0111
max8795a tft-lcd dc-dc converter with operational amplifiers 28 ______________________________________________________________________________________ package information (continued) for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a "+", "#", or "-" in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per - tains to the package regardless of rohs status.
max8795a tft-lcd dc-dc converter with operational amplifiers ______________________________________________________________________________________ 29 package information (continued) for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a "+", "#", or "-" in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per - tains to the package regardless of rohs status.
max8795a tft-lcd dc-dc converter with operational amplifiers 30 ______________________________________________________________________________________ package information (continued) for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a "+", "#", or "-" in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per - tains to the package regardless of rohs status.
max8795a tft-lcd dc-dc converter with operational amplifiers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 31 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 4/07 initial release 0 1 6/07 added lqfp package and g temperature grade versions 1, 2, 6C30 2 12/10 added tqfn version 1C10, 27C30 3 3/11 added automotive-qualified part 1 4 6/11 corrected automotive /v temperature range 1

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